1. Field of the Invention
This invention relates to a data processor that includes a plurality of elements capable of performing concurrent data transformations, and more particularly, to a data processor that includes a tandem arrangement of arithmetic logic units connected by data buses to a register file whereby one unit receives two data items for transformation, while the other unit receives one data item from the register file and a second which is the result from the first unit for a second data transformation thereby permitting two data transformations to be calculated at once.
2. Description of the Prior Art
Known processors for digital computers typically provide a single arithmetic logic unit (ALU) to perform data transformations as well as memory address calculations for data operands and memory address calculations for control flow instructions. The conventional processors are also operable to pass parameter values across procedure boundaries by either storing them on a stack in memory or storing them in a general purpose register. With this arrangement either memory access time or general purpose register space is used.
The known processors typically use a central arithmetic logic unit to calculate the address of the next instruction assembled for execution. Conventionally, an instruction fetch unit (IFU) is utilized to pre-fetch instructions from memory in sequential order so that sequential instructions can be prepared to be issued rapidly. Some instructions specify the address of the next instruction to be executed which need not be the next sequential instruction, such as encountered with control flow instructions. Some control flow instructions may or may not be executed depending on the result of a prior instruction. These are known as conditional control flow instructions.
Most conventional data processors have many instructions which can set condition control flow instructions. In this regard the instruction that most recently sets the condition information prior to a conditional control flow instruction determines the next instruction to be performed. Commonly many instructions can be executed which set condition information that is never used. Also it is known that some processors have single instructions which specify both how to calculate condition information and a conditional control flow action. The conditional control flow action cannot be fully executed until the condition information is calculated by the same instruction.
Therefore, there is a need for a data processor that produces a conditional result followed by several instructions before a conditional control flow instruction. Further there is needed an instruction fetch unit that can detect the control flow instruction, receive a conditional result from the arithmetic logic units and fetch an instruction from a non-sequential location while the arithmetic logic units concurrently continue executing data transformations.
It is also known that only certain classes of algorithms can be fitted to vector instructions suitable for manipulation by a class of computers known as vector computers. It is often necessary to perform manipulations to make a computation "fit" the vector operations on such a computer. Many vector computers use finite-sized vector registers. Data sets must be broken up into segments of this size. Further with this arrangement, very recently computed values cannot be retrieved for the computation of "later" values.
Other machines use memory-to-memory vector operations in which case a similar "threshold", related to the write-to-memory/read-from-memory pipeline length exists. Not all vector operations can be performed on vector computers. In those instances where a value to be computed depends on the value just computed, the value is caught in a torrential current in a pipeline stage of several instructions.
For high level computer languages, such as Ada, vector computers experience difficulty with exception handling. The Ada language requires method exception handlers which are statistically nested within a subroutine.
Difficulty arises because there is no mechanism for inserting constraint checks into vector operations. Since machine checks (such as overflow) are generally not "raised" by the hardware until after the vector operation is complete, nonoptimal vector code must be generated.
Therefore there is need to provide data processing apparatus that performs vector functions without the necessity of incorporating additional hardware with a computer and permit the computer to execute recurrent loops in which a value to be computed depends on the value which was previously computed and which operation cannot be performed on a vector machine.